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SPECIAL ENVIRONMENT 80960CF-30 -25 -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR
Socket and Object Code Compatible with 80960CA Two Instructions Clock Sustained Execution Four 59 Mbytes s DMA Channels with Data Chaining Demultiplexed 32-bit Burst Bus with Pipelining
Y
32-bit Parallel Architecture Two Instructions clock Execution Load Store Architecture Sixteen 32-bit Global Registers Sixteen 32-bit Local Registers Manipulate 64-bit Bit Fields 11 Addressing Modes Full Parallel Fault Model Supervisor Protection Model Fast Procedure Call Return Model Full Procedure Call in 4 clocks On-Chip Register Cache Caches Registers on Call Ret Minimum of 6 Frames provided Up to 15 Programmable Frames On-Chip Instruction Cache 4 Kbyte Two-Way Set Associative 128-bit Path to Instruction Sequencer Cache-Lock Modes Cache-Off Mode On-Chip Data Cache 1 Kbyte Direct-Mapped Write Through 128 bits per Clock Access on Cache Hit Product Grades Available SE3 b 40 C to a 110 C
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
High Bandwidth On-Chip Data RAM 1 Kbytes On-Chip RAM for Data Sustain 128 bits per clock access Four On-Chip DMA Channels 59 Mbytes s Fly-by Transfers 32 Mbytes s Two-Cycle Transfers Data Chaining Data Packing Unpacking Programmable Priority Method 32-Bit Demultiplexed Burst Bus 128-bit Internal Data Paths to and from Registers Burst Bus for DRAM Interfacing Address Pipelining Option Fully Programmable Wait States Supports 8 16 or 32-bit Bus Widths Supports Unaligned Accesses Supervisor Protection Pin Selectable Big or Little Endian Byte Ordering High-Speed Interrupt Controller Up to 248 External Interrupts 32 Fully Programmable Priorities Multi-mode 8-bit Interrupt Port Four Internal DMA Interrupts Separate Non-maskable Interrupt Pin Context Switch in 750 ns Typical
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
January 1995
Order Number 271328-001
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
271328 - 1
Figure 1 80960CF Die Photo
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Special Environment 80960CF-30 -25 -16 32-Bit High Performance Superscalar Processor
CONTENTS
1 0 PURPOSE 2 0 i960 CF PROCESSOR OVERVIEW 2 1 The C-Series Core 2 2 Pipelined Burst Bus 2 3 Flexible DMA Controller 2 4 Priority Interrupt Controller 2 5 Instruction Set Summary 3 0 PACKAGE INFORMATION 3 1 Package Introduction 3 2 Pin Descriptions 3 3 80960CF Pinout 3 4 Mechanical Data 3 5 Package Thermal Specifications 3 6 Stepping Register Information 3 7 Suggested Sources for 80960CF Accessories 4 0 ELECTRICAL SPECIFICATIONS 4 1 Absolute Maximum Ratings 4 2 Operating Conditions 4 3 Recommended Connections 4 4 DC Specifications 4 5 AC Specifications 5 0 RESET BACKOFF AND HOLD ACKNOWLEDGE 6 0 BUS WAVEFORMS PAGE
5 5 6 6 6 6 7 8 8 8 14 18 20 21 21 22 22 22 22 23 24 35 36
CONTENTS
FIGURES Figure 1 Figure 2 Figure 3 Figure 4a Figure 4b Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10a Figure 10b Figure 11 Figure 12a Figure 12b Figure 13 Figure 14 80960CF Die Photo 80960CF Block Diagram Example Pin Description Entry 80960CF PGA Pinout (View from Top Side) 80960CF PGA Pinout (View from Bottom Side) 168-Lead Ceramic PGA Package Dimensions 80960CF PGA Package Thermal Characteristics Measuring 80960CF PGA Case Temperature Register G0 AC Test Load Input and Output Clocks Waveform CLKIN Waveform Output Delay and Float Waveform Input Setup and Hold Waveform NMI XINT7 0 Input Setup and Hold Waveform Hold Acknowledge Timings Bus Back-Off (BOFF) Timings
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2 5 8 16 17 18 20 21 21 30 30 30 31 31 31 32 32
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CONTENTS
Figure 15
PAGE Relative Timings Waveforms 33 Figure 16 Output Delay or Hold vs Load Capacitance 33 Figure 17 Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC 34 Figure 18 ICC vs Frequency and Temperature 34 Figure 19 Cold Reset Waveform 36 Figure 20 Warm Reset Waveform 37 Figure 21 Entering the ONCE State 38 Figure 22a Clock Synchronization in the 2x Clock Mode 39 Figure 22b Clock Synchronization in the 39 1x Clock Mode Figure 23 Non-Burst Non-Pipelined Requests without Wait States 40 Figure 24 Non-Burst Non-Pipelined Read Request with Wait 41 States Figure 25 Non-Burst Non-Pipelined Write Request with Wait States 42 Figure 26 Burst Non-Pipelined Read Request without Wait States 32-Bit Bus 43 Figure 27 Burst Non-Pipelined Read Request with Wait States 32-Bit Bus 44 Figure 28 Burst Non-Pipelined Write Request without Wait States 32-Bit Bus 45 Figure 29 Burst Non-Pipelined Write Request with Wait States 32-Bit Bus 46 Figure 30 Burst Non-Pipelined Read Request with Wait States 16-Bit Bus 47
CONTENTS
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46
Figure 47
Figure 48
PAGE Burst Non-Pipelined Read Request with Wait States 8-Bit Bus 48 Non-Burst Pipelined Read Request without Wait States 32-Bit Bus 49 Non-Burst Pipelined Read Request with Wait States 32-Bit Bus 50 Burst Pipelined Read Request without Wait States 32-Bit Bus 51 Burst Pipelined Read Requests with Wait States 32-Bit Bus 52 Burst Pipelined Read Requests with Wait States 16-Bit Bus 53 Burst Pipelined Read Requests with Wait States 8-Bit Bus 54 Using External READY 55 Terminating a Burst with BTERM 56 BOFF Functional Timing 57 HOLD Functional Timing 57 DREQ and DACK Functional 58 Timing EOP Functional Timing 58 Terminal Count Functional Timing 59 FAIL Functional Timing 59 A Summary of Aligned and Unaligned Transfers for Little Endian Regions 60 A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) 61 Idle Bus Operation 62
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
tions every clock and peak at execution of three instructions per clock A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte s bandwidth to a system's highspeed external memory sub-system In addition the 80960CF's on-chip caching of instructions procedure context and critical program data substantially decouples system performance from the wait states associated with accesses to the system's slower cost sensitive main memory sub-system The 80960CF bus controller also integrates full wait state and bus width control for highest system performance with minimal system design complexity Unaligned access and Big Endian byte order support reduces the cost of porting existing applications to the 80960CF The processor also integrates four complete datachaining DMA channels and a high-speed interrupt controller on-chip The DMA channels perform single-cycle or two-cycle transfers data packing and unpacking and data chaining Block transfers in addition to source or destination synchronized transfers are provided The interrupt controller provides full programmability of 248 interrupt sources into 32 priority levels with a typical interrupt task switch (``latency'') time of 750 ns
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PURPOSE
This document previews electrical characterizations of Intel's i960 CF embedded microprocessor (available in 33 25 and 16 MHz) For a detailed description of any i960 CF processor functional topic other than parametric performance refer to the latest i960 CA Microprocessor Reference Manual (Order No 270710) and the i960 CF Reference Manual Addendum (Order No 272188)
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i960 CF PROCESSOR OVERVIEW
Intel's i960 CF microprocessor is the performance follow-on product to the i960 CA processor The i960 CF product is socket- and object code-compatible with the CA this makes CA-to-CF design upgrades straightforward The i960 CF processor's instruction cache is 4 Kbytes (CA device has 1 Kbyte) CF data cache is 1 Kbyte (CA device has no data cache) This extra cache on the CF product adds a significant performance boost over the CA The 80960CF is object code compatible with the 32-bit 80960 Core Architecture while including Special Function Register extensions to control on-chip peripherals and instruction set extensions to shift 64bit operands and configure on-chip hardware Multiple 128-bit internal busses on-chip instruction caching and a sophisticated instruction scheduler allow the processor to sustain execution of two instruc-
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Figure 2 80960CF Block Diagram 5
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
Demultiplexed Burst Bus to exploit most efficient DRAM access modes Address Pipelining to reduce memory cost while maintaining performance 32- 16- and 8-bit modes for I O interfacing ease Full internal wait state generation to reduce system cost Little and Big Endian support to ease application development Unaligned access support for code portability Three-deep request queue to decouple the bus from the core
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The C-Series Core
The C-Series core is a very high performance microarchitectural implementation of the 80960 Core Architecture The C-Series core can sustain execution of two instructions per clock (66 MIPs at 33 MHz) To achieve this level of performance Intel has incorporated state-of-the-art silicon technology and innovative microarchitectural constructs into the implementation of the C-Series core Factors that contribute to the core's performance include Parallel instruction decoding allows issue of up to three instructions per clock Most instructions execute in a single clock Parallel instruction decode allows sustained simultaneous execution of two single-clock instructions every clock cycle Efficient instruction pipeline minimizes pipeline break losses Register and resource scoreboarding allow simultaneous multi-clock instruction execution Branch look-ahead and prediction allows many branches to execute with no pipeline break Local Register Cache integrated on-chip caches Call Return context Two-way set associative 4 Kbyte integrated instruction cache Direct mapped 1 Kbyte data cache write through write allocate 1 Kbyte integrated Data RAM sustains a fourword (128-bit) access every clock cycle
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Flexible DMA Controller
A four channel DMA controller provides high speed DMA control for data transfers involving peripherals and memory The DMA provides advanced features such as data chaining byte assembly and disassembly and a high performance fly-by mode capable of transfer speed of up to 59 Mbytes per second at 33 MHz The DMA controller features a performance and flexibility which is only possible by integrating the DMA controller and the 80960CF core
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Priority Interrupt Controller
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Pipelined Burst Bus
A 32-bit high performance bus controller interfaces the 80960CF to external memory and peripherals The Bus Control Unit features a maximum transfer rate of 132 Mbytes per second (at 33 MHz) Internally programmable wait states and 16 separately configurable memory regions allow the processor to interface with a variety of memory subsystems with a minimum of system complexity and a maximum of performance The Bus Controller's main features include
A programmable-priority interrupt controller manages up to 248 external sources through the 8-bit external interrupt port The Interrupt Unit also handles the four internal sources from the DMA controller and a single non-maskable interrupt input The 8-bit interrupt port can also be configured to provide individual interrupt sources that are level or edge triggered Interrupts in the 80960CF are prioritized and signaled within 270 ns of the request If the interrupt is of higher priority than the processor priority the context switch to the interrupt routine typically is complete in another 480 ns The interrupt unit provides the mechanism for the low latency and high throughput interrupt service which is essential for embedded applications
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
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Instruction Set Summary
The following table summarizes the 80960CF instruction set by logical groupings See the i960 CA Microprocessor Reference Manual for a complete description of the instruction set Data Movement Load Store Move Load Address Arithmetic Add Subtract Multiply Divide Remainder Modulo Shift Extended Shift Extended Multiply Extended Divide Add with Carry Subtract with Carry Rotate Branch Unconditional Branch Conditional Branch Compare and Branch Logical And Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand Bit Bit Field and Byte Set Bit Clear Bit Not Bit Alter Bit Scan for Bit Span over Bit Extract Modify Scan Byte for Equal
Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Debug Modify Trace Controls Mark Force Mark
Call and Return Call Call Extended Call System Return Branch and Link
Fault Conditional Fault Synchronize Faults
Processor Management Modify Process Controls Modify Arithmetic Controls System Control DMA Control Flush Local Registers
Atomic Atomic Add Atomic Modify
NOTE Instructions marked by ( ) are 80960CF extensions to the 80960 instruction set
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
30 31
PACKAGE INFORMATION Package Introduction
I
Table 1 Pin Description Nomenclature Symbol Input only pin Output only pin Pin can be either an input or output Pins ``must be'' connected as described ) Synchronous Inputs must meet setup and hold times relative to PCLK2 1 for proper operation All outputs are synchronous to PCLK2 1 S(E) Edge sensitive input S(L) Level sensitive input Asynchronous Inputs may be asynchronous to PCLK2 1 A(E) Edge sensitive input A(L) Level sensitive input While the processor's bus is in the Hold Acknowledge or Bus Backoff state the pin H(1) is driven to VCC H(0) is driven to VSS H(Z) floats H(Q) continues to be a valid output While the processor's RESET pin is low the pin R(1) is driven to VCC R(0) is driven to VSS R(Z) floats R(Q) continues to be a valid output Description
This section describes the pins pinouts and thermal characteristics for the 80960CF in the 168-pin Ceramic Pin Grid Array (PGA) package For complete package specifications and information see the Intel Packaging Outlines and Dimensions Guide (Order No 231369)
O IO S(
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Pin Descriptions
The 80960CF pins are described in this section Table 1 presents the legend for interpreting the pin descriptions in the following tables Pins associated with the 32-bit demultiplexed processor bus are described in Table 2 Pins associated with basic processor configuration and control are described in Table 3 Pins associated with the 80960CF DMA Controller and Interrupt Unit are described in Table 4 Figure 3 provides an example pin description table entry ``I O'' signifies that data pins are input-output ``S'' indicates pins are synchronous to PCLK2 1 ``H(Z)'' indicates that these pins float while the processor bus is in a Hold Acknowledge state ``R(Z)'' indicates that the pins also float while RESET is low All pins float while the processor is in the ONCE mode
A(
)
H(
)
R(
)
Name D31 0
Type IO S(L) H(Z) R(Z)
Description DATA BUS carries 32- 16- or 8-bit data quantities depending on bus width configuration The least significant bit of the data is carried on D0 and the most significant on D31 When the bus is configured for 8-bit data the lower 8 data lines D7 0 are used For 16-bit bus widths D15 0 are used For 32-bit bus widths the full data bus is used Figure 3 Example Pin Description Entry
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
Table 2 80960CF Pin Description Name A31 2 Type O S H(Z) R(Z) IO S(L) H(Z) R(Z) O S H(Z) R(1)
External Bus Signals
Description ADDRESS BUS carries the physical address upper 30 bits A31 is the most significant address bit and A2 is the least significant During a bus access A31 2 identify all external addresses to word (4-byte) boundaries The byte enable signals indicate the selected byte in each word During burst accesses A3 and A2 increment to indicate successive data cycles DATA BUS carries 32- 16- or 8-bit data quantities depending on bus width configuration The least significant bit of the data is carried on D0 and the most significant on D31 When the bus is configured for 8-bit data the lower 8 data lines D7 0 are used For 16-bit bus widths D15 0 are used For 32-bit bus widths the full data bus is used BYTE ENABLES select which of the four bytes addressed by A31 2 are active during an access to a memory region configured for a 32-bit data-bus width BE3 applies to D31 24 BE2 applies to D23 16 BE1 applies to D15 8 and BE0 applies to D7 0 32-bit bus BE3 - Byte Enable 3 - enable D31 24 BE2 - Byte Enable 2 - enable D23 16 - Byte Enable 1 - enable D15 8 BE1 BE0 - Byte Enable 0 - enable D7 0 For accesses to a memory region configured for a 16-bit data-bus width the processor directly encodes BE3 BE1 and BE0 to provided BHE A1 and BLE respectively 16-bit bus BE3 BE2 BE1 BE0 - Byte High Enable (BHE) - enable D15 8 - Not used (is driven high or low) - Address Bit 1 (A1) - Byte Low Enable (BLE) - enable D7 0
D31 0
BE3 BE2 BE1 BE0
For accesses to a memory region configured for an 8-bit data bus width the processor directly encodes BE1 and BE0 to provide A1 and A0 respectively 8-bit bus BE3 BE2 BE1 BE0 - Not used (is driven high or low) - Not used (is driven high or low) - Address Bit 1 (A1) - Address Bit 0 (A0)
WR
O S H(Z) R(0) O S H(Z) R(1) I S(L) H(Z) R(Z)
WRITE READ is asserted for read requests and deasserted for write requests The W R signal changes in the same clock cycle as ADS It remains valid for the entire access in non-pipelined regions In pipelined regions W R is not guaranteed valid in the last cycle of a read access ADDRESS STROBE indicates valid address and the start of a new bus access ADS is asserted for the first clock of a bus access
ADS
READY
READY is an input which signals the termination of a data transfer READY is used to indicate that read data on the bus is valid or that a write-data transfer has completed The READY signal works in conjunction with the internally programmed wait-state generator If READY is enabled in a region the pin is sampled after the programmed number of wait-states has expired If the READY pin is deasserted wait states continue to be inserted until READY becomes asserted This is true for the NRAD NRDD NWAD and NWDD wait states The NXDA wait states cannot be extended
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
Table 2 80960CF Pin Description Name BTERM Type I S(L) H(Z) R(Z)
External Bus Signals (Continued) Description
BURST TERMINATE The burst terminate signal breaks up a burst access and causes another address cycle to occur The BTERM signal works in conjunction with the internally programmed wait-state generator If READY and BTERM are enabled in a region the BTERM pin is sampled after the programmed number of wait states has expired When BTERM is asserted a new ADS signal is generated and the access is completed The READY input is ignored when BTERM is asserted BTERM must be externally synchronized to satisfy the BTERM setup and hold times WAIT indicates internal wait state generator status WAIT is asserted when wait states are being caused by the internal wait state generator and not by the READY or BTERM inputs WAIT can be used to derive a write-data strobe WAIT can also be thought of as a READY output that the processor provides when it is inserting wait states BURST LAST indicates the last transfer in a bus access BLAST is asserted in the last data transfer of burst and non-burst accesses after the wait state counter reaches zero BLAST remains asserted until the clock following the last cycle of the last data transfer of a bus access If the READY or BTERM input is used to extend wait states the BLAST signal remains asserted until READY or BTERM terminates the access DATA TRANSMIT RECEIVE indicates direction for data transceivers DT R is used in conjunction with DEN to provide control for data transceivers attached to the external bus When DT R is asserted the signal indicates that the processor receives data Conversely when deasserted the processor sends data DT R changes only while DEN is high DATA ENABLE indicates data cycles in a bus request DEN is asserted at the start of the bus request first data cycle and is deasserted at the end of the last data cycle DEN is used in conjunction with DT R to provide control for data transceivers attached to the external bus DEN remains asserted for sequential reads from pipelined memory regions DEN is deasserted when DT R changes BUS LOCK indicates that an atomic read-modify-write operation is in progress LOCK may be used to prevent external agents from accessing memory which is currently involved in an atomic operation LOCK is asserted in the first clock of an atomic operation and deasserted in the clock cycle following the last bus access for the atomic operation To allow the most flexibility for a memory system enforcement of locked accesses the processor acknowledges a bus hold request when LOCK is asserted The processor performs DMA transfers while LOCK is active HOLD REQUEST signals that an external agent requests access to the external bus The processor asserts HOLDA after completing the current bus request HOLD HOLDA and BREQ are used together to arbitrate access to the processor's external bus by external bus agents BUS BACKOFF The backoff pin when asserted suspends the current access and causes the bus pins to float When deasserted the ADS signal is asserted on the next clock cycle and the access is resumed
WAIT
O S H(Z) R(1) O S H(Z) R(0)
BLAST
DT R
O S H(Z) R(0) O S H(Z) R(1) O S H(Z) R(1)
DEN
LOCK
HOLD
I S(L) H(Z) R(Z) I S(L) H(Z) R(Z)
BOFF
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
Table 2 80960CF Pin Description Name HOLDA Type O S H(1) R(Q)
External Bus Signals (Continued) Description
HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relinquished control of the external bus When HOLDA is asserted the external address bus data bus and bus control signals are floated HOLD BOFF HOLDA and BREQ are used together to arbitrate access to the processor's external bus by external bus agents Since the processor grants HOLD requests and enters the Hold Acknowledge state even while RESET is asserted HOLDA pin state is independent of the RESET pin BUS REQUEST is asserted when the bus controller has a request pending BREQ can be used by external bus arbitration logic in conjunction with HOLD and HOLDA to determine when to return mastership of the external bus to the processor DATA OR CODE is asserted for a data request and deasserted for instruction requests D C has the same timing as W R
BREQ
O S H(Q) R(0) O S H(Z) R(Z) O S H(Z) R(Z) O S H(Z) R(Z)
DC
DMA
DMA ACCESS indicates whether the bus request was initiated by the DMA controller DMA is asserted for any DMA request DMA is deasserted for all other requests SUPERVISOR ACCESS indicates whether the bus request is issued while in supervisor mode SUP is asserted when the request has supervisor privileges and is deasserted otherwise SUP can be used to isolate supervisor code and data structures from non-supervisor requests Table 3 80960CF Pin Description Processor Control Signals Description RESET causes the chip to reset When RESET is asserted all external signals return to the reset state When RESET is deasserted initialization begins When the 2-x clock mode is selected RESET must remain asserted for 16 PCLK2 1 cycles before being deasserted in order to guarantee correct processor initialization When the 1-x clock mode is selected RESET must remain asserted for 10 000 PCLK2 1 cycles before being deasserted in order to guarantee correct initialization The CLKMODE pin selects 1-x or 2-x input clock division of the CLKIN pin The processor's Hold Acknowledge bus state functions while the chip is reset If the processor's bus is in the Hold Acknowledge state when RESET is asserted the processor will internally reset but maintains the Hold Acknowledge state on external pins until the Hold request is removed If a hold request is made while the processor is in the reset state the processor bus grants HOLDA and enters the Hold Acknowledge state FAIL indicates failure of the processor's self-test performed at initialization When RESET is deasserted and the processor begins initialization the FAIL pin is asserted An internal self-test is performed as part of the initialization process If this self-test passes the FAIL pin is deasserted otherwise it remains asserted The FAIL pin is reasserted while the processor performs an external bus self-confidence test If this self-test passes the processor deasserts the FAIL pin and branches to the user's initialization routine otherwise the FAIL pin remains asserted Internal self-test and the use of the FAIL pin can be disabled with the STEST pin
SUP
Name RESET
Type I A(L) H(Z) R(Z) N(Z)
FAIL
O S H(Q) R(0)
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Table 3 80960CF Pin Description Name STEST Type I S(L) H(Z) R(Z) I A(L) H(Z) R(Z)
Processor Control Signals (Continued) Description
SELF TEST causes the processor's internal self-test feature to be enabled or disabled at initialization STEST is read on the rising edge of RESET When asserted the processor's internal self-test and external bus confidence tests are performed during processor initialization When deasserted only the external bus confidence tests are performed during initialization ON CIRCUIT EMULATION causes all outputs to be floated when asserted ONCE is continuously sampled while RESET is low and is latched on the rising edge of RESET To place the processor in the ONCE state (1) assert RESET and ONCE (order does not matter) (2) wait for at least 16 CLKIN periods in 2-x mode or 10 000 CLKIN periods in 1-x mode after VCC and CLKIN are within operating specifications (3) deassert RESET (4) wait at least 32 CLKIN periods (The processor is now latched in the ONCE state as long as RESET is high ) To exit the ONCE state bring VCC and CLKIN to operating conditions then assert RESET and bring ONCE high prior to deasserting RESET CLKIN must operate within the specified operating conditions of the processor until step 4 above is completed The CLKIN may then be changed to DC to achieve the lowest possible ONCE mode leakage current ONCE can be used by emulator products or for board testers to effectively make an installed processor transparent in the board
ONCE
CLKIN
I A(E) H(Z) R(Z) I A(L) H(Z) R(Z)
CLOCK INPUT is an input for the external clock needed to run the processor The external clock is internally divided as prescribed by the CLKMODE pin to produce PCLK2 1 CLOCK MODE selects the division factor applied to the external clock input (CLKIN) When CLKMODE is high CLKIN is divided by one to create PCLK2 1 and the processor's internal clock When CLKMODE is low CLKIN is divided by two to create PCLK2 1 and the processor's internal clock CLKMODE should be tied high or low in a system as the clock mode is not latched by the processor If left unconnected the processor internally pulls the CLKMODE pin low enabling the 2-x clock mode PROCESSOR OUTPUT CLOCKS provide a timing reference for all inputs and outputs of the processor All inputs and output timings are specified in relation to PCLK2 and PCLK1 PCLK2 and PCLK1 are identical signals Two output pins are provided to allow flexibility in the system's allocation of capacitive loading on the clock PCLK2 1 may also be connected at the processor to form a single clock signal GROUND connections consist of 24 pins which must be connected externally to a VSS board plane POWER connections consist of 24 pins which must be connected externally to a VCC board plane VCCPLL is a separate VCC supply pin for the phase lock loop used in 1x clock mode Connecting a simple low pass filter to VCCPLL may help reduce clock jitter (TCP) in noisy environments Otherwise VCCPLL should be connected to VCC NO CONNECT pins must not be connected in a system
CLKMODE
PCLK2 PCLK1
O S H(Q) R(Q)
VSS VCC VCCPLL
NC
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Table 4 80960CF Pin Description Name DREQ3 DREQ2 DREQ1 DREQ0 DACK3 DACK2 DACK1 DACK0 EOP3 EOP2 EOP1 EOP0 TC3 TC2 TC1 TC0 Type I A(L) H(Z) R(Z) O S H(1) R(1) IO A(L) H(Z Q) R(Z)
DMA and Interrupt Unit Control Signals Description
DMA REQUEST causes a DMA transfer to be requested Each of the four signals request a transfer on a single channel DREQ0 requests channel 0 DREQ1 requests channel 1 etc When two or more channels are requested simultaneously the channel with the highest priority is serviced first Channel priority mode is programmable DMA ACKNOWLEDGE indicates that a DMA transfer is being executed Each of the four signals acknowledge a transfer for a single channel DACK0 acknowledges channel 0 DACK1 acknowledges channel 1 etc DACK3 0 are asserted when the requesting device of a DMA is accessed END OF PROCESS TERMINAL COUNT can be programmed as either an input (EOP3 0) or as an output (TC3 0) but not both Each pin is individually programmable When programmed as an input EOPx causes the termination of a current DMA transfer for the channel corresponding to the EOPx pin EOP0 corresponds to channel 0 EOP1 corresponds to channel 1 etc When a channel is configured for source and destination chaining the EOP pin for that channel causes termination of only the current buffer transferred and causes the next buffer to be transferred EOP3 0 are asynchronous inputs When programmed as an output the channel's TCx pin indicates that the channel byte count has reached 0 and a DMA has terminated TCx is driven with the same timing as DACKx during the last DMA transfer for a buffer If the last bus request is executed as multiple bus accesses TCx remains asserted for the entire bus request
XINT7 XINT6 XINT5 XINT4 XINT3 XINT2 XINT1 XINT0
I A(E L) H(Z) R(Z)
EXTERNAL INTERRUPT PINS cause interrupts to be requested These pins can be configured in three modes In Dedicated Mode each pin is a dedicated external interrupt source Dedicated inputs can be individually programmed to be level (low) or edge (falling) activated In Expanded Mode the 8 pins act together as an 8-bit vectored interrupt source The interrupt pins in this mode are level activated Since the interrupt pins are active low the vector number requested is the one's complement of the positive logic value place on the port This eliminates glue logic to interface to combinational priority encoders which output negative logic In Mixed Mode XINT7 5 are dedicated sources and XINT4 0 act as the 5 most significant bits of an expanded mode vector The least significant bits are set to 010 internally NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur NMI is the highest priority interrupt recognized NMI is an edge (falling) activated source
NMI
I A(E) H(Z) R(Z)
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80960CF pinout as viewed from the top side of the component (i e pins facing down) Figure 4b shows the complete 80960CF pinout as viewed from the pin-side of the package (i e pins facing up) See Section 4 0 Electrical Specifications for specifications and recommended connections
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80960CF Pinout
3 3 1 80960CF PGA PINOUT Tables 5 and 6 list the 80960CF pin names with package location Figure 4-a depicts the complete
Table 5 PGA Pin Name with Package Location (Signal Order) Address Bus
Name A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4
Location S15 Q13 R14 Q14 S16 R15 S17 Q15 R16 R17 Q16 P15 P16 Q17 P17 N16 N17 M17
L16 L17 K17 J17 H17 G17 G16 F17 E17 E16
Data Bus Name Location D31 R03 D30 Q05 D29 S02 D28 Q04 D27 R02 D26 Q03 D25 S01 D24 R01 D23 Q02 D22 P03 D21 Q01 D20 P02 D19 P01 D18 N02 D17 N01 D16 M01 D15 L01 D14 L02 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 K01 J01 H01 H02 G01 F01 E01 F02 D01 E02
Bus Control Name Location BE3 S05 BE2 S06 BE1 S07 BE0 R09 WR ADS READY BTERM WAIT BLAST DT R DEN LOCK HOLD HOLDA BREQ DC DMA SUP S10
Processor Control Name Location RESET A16 FAIL STEST ONCE A02 B02
IO Name Location DREQ3 A07 DREQ2 B06 DREQ1 A06 DREQ0 B05 DACK3 A10 A09 A08 B08 A11 A12 A13 A14 C17 C16 B17 C15 B16 A17 A15 B15 D15
C03 C13 C14 B14 B13 VSS
DACK2 DACK1 DACK0 EOP TC0 EOP TC1 EOP TC2 EOP TC3 XINT7 XINT6 XINT5 XINT4 XINT3 XINT2 XINT1 XINT0 NMI
R06 CKLIN S03 R04 S12 S08 S11 S09 S14 R05 S04 R13 S13 R12 Q12 CLKMODE PCLK1 PCLK2
Location C07 C08 C09 C10 C11 C12 F15 G03 G15 H03 H15 J03 J15 K03 K15 L03 L15 M03 M15 Q07 Q08 Q09 Q10 Q11
VCC
Location B07 B09 B11 B12 C06 E15 F03 F16 G02 H16 J02 J16 K02 K16 M02 M16 N03 N15 Q06 R07 R08 R10 R11
VCCPLL B10 No Connect
A3 A2
D17 D16
D3 D2 D1
C01 D02 C02
BOFF
B01
Location
A01 A03 A04 A05 B03 B04 C04 C05 D03
D0 14
E03
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SPECIAL ENVIRONMENT 80960CF-30 -25 -16
Table 6 PGA Pin Name with Package Location (Pin Order) Address Bus Location Name A01 NC A02 FAIL A03 NC A04 NC A05 NC A06 DREQ1 A07 DREQ3 A08 DACK1 A09 DACK2 A10 DACK3 A11 EOP TC0 A12 EOP TC1 A13 EOP TC2 A14 EOP TC3 A15 XINT1 A16 RESET A17 XINT2 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 BOFF STEST NC NC DREQ0 DREQ2 VCC DACK0 VCC VCCPLL VCC VCC PCLK2 PCLK1 XINT0 XINT3 XINT5 Data Bus Location Name C01 D3 C02 D1 C03 ONCE C04 NC C05 NC C06 VCC C07 VSS C08 VSS C09 VSS C10 VSS C11 VSS C12 VSS C13 CLKIN C14 CLKMODE C15 XINT4 C16 XINT6 C17 XINT7 D01 D02 D03 D15 D16 D17 E01 E02 E03 E15 E16 E17 F01 F02 F03 F15 F16 F17 D5 D2 NC NMI A2 A3 D7 D4 D0 VCC A4 A5 D8 D6 VCC VSS VCC A6 Bus Control Location Name G01 D9 G02 VCC G03 VSS G15 VSS G16 A7 G17 A8 H01 H02 H03 H15 H16 H17 J01 J02 J03 J15 J16 J17 K01 K02 K03 K15 K16 K17 L01 L02 L03 L15 L16 L17 D11 D10 VSS VSS VCC A9 D12 VCC VSS VSS VCC A10 D13 VCC VSS VSS VCC A11 D15 D14 VSS VSS A13 A12 Processor Control Location Name M01 D16 M02 VCC M03 VSS M15 VSS M16 VCC M17 A14 N01 N02 N03 N15 N16 N17 P01 P02 P03 P15 P16 P17 Q01 Q02 Q03 Q04 Q05 Q06 Q07 Q08 Q09 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 D17 D18 VCC VCC A16 A15 D19 D20 D22 A20 A19 A17 D21 D23 D26 D28 D30 VCC VSS VSS VSS VSS VSS SUP A30 A28 A24 A21 A18 IO Location Name R01 D24 R02 D27 R03 D31 R04 BTERM R05 HOLD R06 ADS R07 VCC R08 VCC R09 BE0 R10 VCC R11 VCC R12 DMA R13 BREQ R14 A29 R15 A26 R16 A23 R17 A22 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 D25 D29 READY HOLDA BE3 BE2 BE1 BLAST DEN WR DT R WAIT DC LOCK A31 A27 A25
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Figure 4a 80960CF PGA Pinout (View from Top Side)
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Figure 4b 80960CF PGA Pinout (View from Bottom Side)
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Mechanical Data
3 4 1 CERAMIC PGA PACKAGE
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Family Ceramic Pin Grid Array Package Symbol Min A A1 A2 A3 B D D1 e1 L N S1 ISSUE 1 52 IWS 3 56 0 64 23 1 14 0 43 44 07 40 51 2 29 2 54 168 2 54 REV X 7 15 88 0 060 Millimeters Max 4 57 1 14 0 30 1 40 0 51 44 83 40 77 2 79 3 30 SOLID LID SOLID LID Notes Min 0 140 0 025 0 110 0 045 0 017 1 735 1 595 0 090 0 100 168 0 100 Inches Max 0 180 0 045 0 140 0 055 0 020 1 765 1 605 0 110 0 130 SOLID LID SOLID LID Notes
Figure 5 168-Lead Ceramic PGA Package Dimensions
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Table 7 Ceramic PGA Package Dimension Symbols Letter or Symbol A A1 A2 A3 B D D1 e1 L S1 Description of Dimensions Distance from seating plane to highest point of body Distance between seating plane and base plane (lid) Distance from base plane to highest point of body Distance from seating plane to bottom of body Diameter of terminal lead pin Largest overall package dimension of length A body length dimension outer lead center to outer lead center Linear spacing between true lead position centerlines Distance from seating plane to end of lead Other body dimension outer lead center to edge of body
NOTES 1 Controlling dimension millimeter 2 Dimension ``e1'' (``e'') is non-cumulative 3 Seating plane (standoff) is defined by P C board hole size 0 0415 - 0 0430 inch 4 Dimensions ``B'' ``B1'' and ``C'' are nominal 5 Details of Pin 1 identifier are optional
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Table 8 shows the maximum TA allowable (without exceeding TC) at various airflows and operating frequencies (fPCLK) Note that TA is greatly improved by attaching fins or a heat sink to the package P (the maximum power consumption) is calculated by using the typical ICC as tabulated in Section 4 4 DC Specifications and VCC of 5V
35
Package Thermal Specifications
The 80960CF is specified for operation when TC (the case temperature) is within the range of b 40 C- a 110 C TC may be measured in any environment to determine whether the 80960CF is within specified operating range The case temperature is measured at the center of the top surface opposite the pins Refer to Figure 7 TA (the ambient temperature) can be calculated from iCA (thermal resistance from case to ambient) with the following equation
TA e TC b P iCA
Table 8 Maximum TA at Various Airflows In C (PGA Package Only) Airflow-ft min (m sec) fPCLK (MHz) 33 25 16 33 25 16 0 (0) 38 50 63 18 34 51 200 (1 01) 57 65 74 33 46 60 400 (2 03) 74 79 84 47 57 68 600 (3 04) 76 81 86 57 65 74 800 (4 06) 81 85 89 66 72 80 1000 (5 07) 84 87 90 67 74 81
TA with Heat Sink TA without Heat Sink
0 285 high unidirectional heat sink (Al alloy 6061 50 mil fin width 150 mil center-to-center fin spacing)
PGA Thermal Resistance Airflow Parameter i Junction-to-Case (Case Measured as shown in Figure 7) i Case-to-Ambient (No Heatsink) i Case-to-Ambient (with Unidirectional) Heatsink) 0 (0) 15 200 (1 01) 15
C Watt ft min (m sec) 600 (3 07) 15 800 (4 06) 15 1000 (5 07) 15
400 (2 03) 15
17
14
11
9
71
66
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13
9
55
50
39
34
NOTES 1 This table applies to 80960CF PGA plugged into socket or soldered directly into board 2 iJA e iJC a iCA 3 iJ-CAP e 4 C W (approx ) iJ-PIN e 4 C W (inner pins) (approx ) iJ-PIN e 8 C W (outer pins) (approx ) 0 285 high unidirectional heat sink (Al alloy 6061 50 mil fin width 150 mil center-to-center fin spacing)
Figure 6 80960CF PGA Package Thermal Characteristics
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3 7 Suggested Sources for 80960CF Accessories
The following are some suggested sources of accessories for the 80960CF They are neither an endorsement of any kind nor a warranty of the performance of any of the listed products and or companies Sockets 1 3M Textool Test and Interconnection Products Department P O Box 2963 Austin TX 78769-2963 2 Augat Inc Interconnection Products Group 33 Perry Avenue P O Box 779 Attleboro MA 02703 (508) 222-2202 3 Concept Manufacturing Inc (Decoupling Sockets) 43024 Christy Street Fremont CA 94538 (415) 651-3804 Heat Sinks Fins 1 Thermalloy Inc 2021 West Valley View Lane Dallas TX 75381-0839 (214) 243-4321 2 E G G Division 60 Audubon Road Wakefield MA 01880 (617) 245-5900
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Figure 7 Measuring 80960CF PGA Case Temperature
3 6 Stepping Register Information
Upon Reset Register G0 contains die stepping information The following figure shows how G0 is configured The most significant byte contains an ASCII 0 The upper middle byte contains an ASCII C The lower middle byte contains an ASCII F The least significant byte contains the stepping number in ASCII G0 retains this information until it is written over by the user program Table 9 contains a cross reference of the number in the least significant byte of register G0 to the die stepping number
ASCII DECIMAL
00 0 MSB
43 C
46 F
Stepping Number Stepping Number LSB
Figure 8 Register G0 Table 9 Die Stepping Cross Reference G0 Least Significant Byte 01 02 03 04 05 Die Stepping A B C D E
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40
ELECTRICAL SPECIFICATIONS
4 1 Absolute Maximum Ratings
Parameter Storage Temperature Case Temperature Under Bias(2) Supply Voltage wrt VSS Voltage on Other pins wrt VSS Maximum Rating
b 65 C to a 150 C b 40 C to a 125 C b 0 5V to a 6 5V b 0 5V to VCC a 0 5V
NOTICE This data sheet contains information on products in the sampling and initial production phases of development It is valid for the devices indicated in the revision history The specifications are subject to change without notice
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
42
Operating Conditions
Operating Conditions (80960CF-33 -25 -16) Parameter Supply Voltage 80960CF-30 80960CF-25 80960CF-16 80960CF-30 80960CF-25 80960CF-16 80960CF-30 80960CF-25 80960CF-16 PGA Package Min 4 75 4 50 4 50 0 0 0 8 8 8
b 40
Symbol VCC
Max 5 25 5 50 5 50 60 6 50 32 30 3 25 16
a 110
Units V MHz MHz MHz MHz MHz MHz C
Notes
fCLK2x
Input Clock Frequency (2-x Mode)
fCLK1x
Input Clock Frequency (1-x Mode)
(1)
TC
Case Temperature Under Bias 80960CF-30 -25 -16
NOTES (1) When in the 1-x input clock mode CLKIN is an input to an internal phase-locked loop and must maintain a minimum frequency of 8 MHz for proper processor operation However in the 1-x Mode CLKIN may still be stopped when the processor either is in a reset condition or is reset If CLKIN is stopped the specified RESET low time must be provided once CLKIN restarts and has stabilized (2) Case temperatures are ``Instant On''
4 3 Recommended Connections
Power and ground connections must be made to multiple VCC and VSS (GND) pins Every 80960CFbased circuit board should include power (VCC) and ground (VSS) planes for power distribution Every VCC pin must be connected to the power plane and every VSS pin must be connected to the ground plane Pins identified as ``N C '' must not be connected in the system Liberal decoupling capacitance should be placed near the 80960CF The processor can cause transient power surges when its numerous output buffers transition particularly when connected to large capacitive loads
Low inductance capacitors and interconnects are recommended for best high frequency electrical performance Inductance can be reduced by shortening board traces between the processor and decoupling capacitors as much as possible Capacitors specifically designed for PGA packages will offer the lowest possible inductance For reliable operation always connect unused inputs to an appropriate signal level In particular any unused interrupt (XINT NMI) or DMA (DREQ) input should be connected to VCC through a pull-up resistor as should BTERM if not used Pull-up resistors should be in the range of 20 KX for each pin tied high If READY or HOLD are not used the unused input should be connected to ground N C pins must always remain unconnected Refer to the i960 CA Microprocessor Reference Manual for more information
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44
DC Specifications
DC Characteristics (80960CF-30 -25 -16 under the conditions described in Section 4 2 Operating Conditions )
Symbol VIL VIH VOL VOH VILR VIHR ILI1
Parameter Input Low Voltage for all pins except RESET Input High Voltage for all pins except RESET Output Low Voltage Output High Voltage IOH e b 1mA IOH e b 200mA
Min
b0 3
Max 08 VCC a 0 3 0 45
Units V V V V V
Notes
20
IOL e 5 mA
24 VCC b 0 5
b03
Input Low Voltage for RESET Input High Voltage for RESET Input Leakage Current for each pin except BTERM ONCE DREQ3 0 STEST EOP3 0 TC3 0 NMI XINT7 0 READY HOLD BOFF CLKMODE Input Leakage Current for BTERM ONCE DREQ3 0 STEST EOP3 0 TC3 0 NMI XINT7 0 BOFF Input Leakage Current for READY HOLD CLKMODE Output Leakage Current Supply Current (80960CF-30) ICC Max ICC Typ Supply Current (80960CF-25) ICC Max ICC Typ Supply Current (80960CF-16) ICC Max ICC Typ ONCE-mode Supply Current Input Capacitance for CLKIN RESET ONCE READY HOLD DREQ3 0 BOFF XINT7 0 NMI BTERM CLKMODE Output Capacitance of each output pin I O Pin Capacitance
15 VCC a 0 3
V V
35
g15
mA
0V s VIN s VCC (1)
ILI2
0 0
b 325
mA mA mA mA
VIN e 0 45V (2) VIN e 2 4V (3) 0 45V s VOUT s VCC (4) (5) (4) (5) (4) (5)
ILI3 ILO ICC
500
g15
1150 960 950 775 750 575 150
ICC
mA
ICC
mA mA
IONCE CIN
0
12 12 12
pF pF pF
FC e 1 MHz FC e 1 MHz (6) FC e 1 MHz
COUT CI O
NOTES (1) No Pull-up or pull-down (2) These pins have internal pullup resistors (3) These pins have internal pulldown resistors (4) Measured at worst case frequency VCC and temperature with device operating and outputs loaded to the test conditions described in Section 4 5 1 AC Test Conditions (5) ICC Typical is not tested (6) Output Capacitance is the capacitive load of a floating output (7) CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted
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4 5 AC Specifications
AC Characteristics 80960CF-30 (80960CF-30 only under the conditions described in Section 4 2 Operating Conditions and Section 4 5 1 AC Test Conditions ) See notes which follow this table
Symbol INPUT CLOCK(10) TF TC TCS TCH TCL TCR TCF TCP T TPH TPL TPR TPF TOV TOH CLKIN Frequency CLKIN Period CLKIN Period Stability CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time CLKIN to PCLK2 1 Delay PCLK2 1 Period PCLK2 1 High Time PCLK2 1 Low Time PCLK2 1 Rise Time PCLK2 1 Fall Time Output Valid Delay Output Hold TOV1 TOH1 A31 2 BE3 0 TOV2 TOH2 TOV3 TOH3 ADS TOV4 TOH4 WR TOV5 TOH5 D C SUP DMA BLAST WAIT TOV6 TOH6 TOV7 TOH7 DEN TOV8 TOH8 HOLDA BREQ LOCK TOV9 TOH9 DACK3 0 TOV10 TOH10 TOV11 TOH11 D31 0 TOV12 TOH12 DT R TOV13 TOH13 FAIL EOP TC3 0 TOV14 TOH14 Output Float for all outputs Input Setup TIS1 TIS2 TIS3 TIS4 Input Hold TIH1 TIH2 TIH3 TIH4 In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) (T 2) b 2 (T 2) b 2 1 1 In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) 6 6 6 6 0 0
b2
Parameter
Min 0 33 16 5
Max 60 6 125 %
g0 1%
Units MHz ns ns D ns ns ns ns ns ns ns ns ns ns
Notes (1) (1 12) (1) (1 13) (1 12) (1) (1 12) (1) (1) (1) (1 3 13 14) (1 3) (1 13) (1 3) (1 13) (1 13) (1 3) (1 3) (6 11)
62 5 % 62 5 % 6 6 2 25 TC 2TC T2 T2 4 4
OUTPUT CLOCKS(9) 2
ns ns ns ns
SYNCHRONOUS OUTPUTS(10) 3 3 6 3 4 5 3 4 4 4 3 T 2a3 2 3 3 14 16 18 18 16 16 16 16 16 18 16 T 2 a 14 14 18 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(6 11) (6)
TOF TIS
SYNCHRONOUS INPUTS(10) D31 0 BOFF BTERM READY HOLD D31 0 BOFF BTERM READY HOLD 3 17 7 7 5 5 2 3 ns ns ns ns ns ns ns ns (1 11) (1 11) (1 11) (1 11) (1 11) (1 11) (1 11) (1 11)
TIH
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AC Characteristics 80960CF-30 (80960CF-30 only under the conditions described in Section 4 2 Operating Conditions and Section 4 5 1 AC Test Conditions ) See notes which follow this table (Continued)
Symbol TAVSH1 TAVSH2 TAVEL1 TAVEL2 TNLQV TDVNH TNLNH TNHQX TEHTV TTVEL TIS5 TIH5 TIS6 TIH6 TIS7 TIH7 TIS8 TIH8 Parameter A31 2 Valid to ADS Rising BE3 0 W R SUP D C DMA DACK3 0 Valid to ADS Rising A31 2 Valid to DEN Falling BE3 0 W R SUP INST DMA DACK3 0 Valid to DEN Falling WAIT Falling to Output Data Valid Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising Output Data Hold after WAIT Rising DT R Hold after DEN High DT R Valid to DEN Falling RESET Input Setup (2x Clock Mode) RESET Input Hold (2x Clock Mode) DREQ3 0 Input Setup DREQ3 0 Input Hold XINT7 0 NMI Input Setup XINT7 0 NMI Input Hold RESET Input Setup (1x Clock Mode) RESET Input Hold (1x Clock Mode) T 2b6 T 2b4 6 5 12 7 7 3 3 T 4a1 N Tb6 N Tg4 (N a 1) T b 6 (N a 1) T a 6 % T 2a4 Min Tb4 Tb6 Tb4 Tb6
g6
Max Ta4 Ta6 Ta4 Ta6 N Ta6
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes
RELATIVE OUTPUT TIMINGS(9 7)
(4) (4) (5) (6) (7) (14) (14) (8) (8) (8) (8) (15) (15)
RELATIVE INPUT TIMINGS(7)
NOTES 1 See Section 4 5 2 AC Timing Waveforms for waveforms and definitions 2 See Figure 22 for capacitive derating information for output delays and hold times 3 See Figure 23 for capacitive derating information for rise and fall times 4 Where N is the number of NRAD NRDD NWAD or NWDD wait states that are programmed in the Bus Controller Region Table When there are no wait states in an access WAIT never goes active 5 N e Number of wait states inserted with READY 6 Output Data and or DT R may be driven indefinitely following a cycle if there is no subsequent bus activity 7 See Notes 1 2 and 3 8 Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in order to be recognized and for proper operation However to guarantee recognition of the input at a particular edge of PCLK2 1 the setup times shown must be met Asynchronous inputs must be active for at least two consecutive PCLK2 1 rising edges to be seen by the processor 9 These specifications are guaranteed by the processor 10 These specifications must be met by the system for proper operation of the processor 11 This timing is dependent upon the loading of PCLK2 1 Use the derating curves of Section 4 5 3 to adjust the timing for PCLK2 1 loading 12 In the 1-x input clock mode the maximum input clock period is limited to 125 ns while the processor is operating When the processor is in reset the input clock may stop even in 1-x mode 13 When in the 1-x input clock mode these specifications assume a stable input clock with a period variation of less than g0 1% between adjacent cycles 14 In 2x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup and hold times to the falling edge of the CLKIN (See Figure 28a ) 15 In 1x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must be deasserted while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN (See Figure 28b )
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AC Characteristics 80960CF-25 (80960CF-25 only under the conditions described in Section 4 2 Operating Conditions and Section 4 5 1 AC Test Conditions )
Symbol TF TC TCS TCH TCL TCR TCF TCP T TPH TPL TPR TPF TOV TOH CLKIN Frequency CLKIN Period CLKIN Period Stability CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time OUTPUT CLOCKS(9) CLKIN to PCLK2 1 Delay PCLK2 1 Period PCLK2 1 High Time PCLK2 1 Low Time PCLK2 1 Rise Time PCLK2 1 Fall Time Output Valid Delay Output Hold TOV1 TOH1 TOV2 TOH2 TOV3 TOH3 TOV4 TOH4 TOV5 TOH5 TOV6 TOH6 TOV7 TOH7 TOV8 TOH8 TOV9 TOH9 TOV10 TOH10 TOV11 TOH11 TOV12 TOH12 TOV13 TOH13 TOV14 TOH14 Output Float for all outputs Input Setup TIS1 TIS2 TIS3 TIS4 Input Hold TIH1 TIH2 TIH3 TIH4 In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) (T 2) b 3 (T 2) b 3 1 1 SYNCHRONOUS OUTPUTS(10) (6 11) A31 2 BE3 0 ADS WR D C SUP DMA BLAST WAIT DEN HOLDA BREQ LOCK DACK3 0 D31 0 DT R FAIL EOP3 0 TC3 0 3 3 6 3 4 5 3 4 4 4 3 T 2a3 2 3 3 SYNCHRONOUS INPUTS(10) TIS D31 0 BOFF BTERM READY HOLD D31 0 BOFF BTERM READY HOLD 5 19 9 9 5 7 2 5 ns ns ns ns ns ns ns ns (1 11) (1 11) (1 11) (1 11) (1 11) (1 11) (1 11) (1 11) 16 18 20 20 18 18 18 18 18 20 18 T 2 a 16 16 20 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
b2
Parameter INPUT CLOCK(10)
Min 0
Max 50 125 %
g0 1%
Units MHz ns ns D ns ns ns ns ns ns ns ns ns ns
Notes (1) (1 12) (1) (1 13) (1 12) (1) (1 12) (1) (1) (1) (1 3 13 14) (1 3) (1 13) (1 3) (1 13) (1 13) (1 3) (1 3)
In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x)
40 20 8 8 8 8 0 0
62 5 % 62 5 % 6 6 2 25 TC 2TC T2 T2 4 4
2
ns ns ns ns
(6 11) (6)
TOF
TIH
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AC Characteristics 80960CF-25 (80960CF-25 only under the conditions described in Section 4 2 Operating Conditions and Section 4 5 1 AC Test Conditions ) (Continued)
Symbol TAVSH1 TAVSH2 TAVEL1 TAVEL2 TNLQV TDVNH TNLNH TNHQX TEHTV TTVEL TIS5 TIH5 TIS6 TIH6 TIS7 TIH7 TIS8 TIH8 Parameter A31 2 Valid to ADS Rising BE3 0 W R SUP D C DMA DACK3 0 Valid to ADS Rising A31 2 Valid to DEN Falling BE3 0 W R SUP INST DMA DACK3 0 Valid to DEN Falling WAIT Falling to Output Data Valid Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising Output Data Hold after WAIT Rising DT R Hold after DEN High DT R Valid to DEN Falling RESET Input Setup (2x Clock Mode RESET Input Hold (2x Clock Mode) DREQ3 0 Input Setup DREQ3 0 Input Hold XINT7 0 NMI Input Setup XINT7 0 NMI Input Hold RESET Input Setup (1x Clock Mode) RESET Input Hold (1x Clock Mode) T 2b6 T 2b4 RELATIVE INPUT TIMINGS(7) 8 7 14 9 9 5 3 T 4a1 ns ns ns ns ns ns ns ns (14) (14) (8) (8) (8) (8) (15) (15) N Tb6 N Tg4 (N a 1) T b 6 (N a 1) T a 6 % T 2a4 Min RELATIVE OUTPUT TIMINGS(9 7) Tb4 Tb6 Tb4 Tb6
g6
Max Ta4 Ta6 Ta4 Ta6 N Ta6
Units ns ns ns ns ns ns ns ns ns ns
Notes
(4) (4) (5) (6) (7)
NOTES (1) See Section 4 5 2 AC Timing Waveforms for waveforms and definitions (2) See Figure 22 for capacitive derating information for output delays and hold times (3) See Figure 23 for capacitive derating information for rise and fall times (4) Where N is the number of NRAD NRDD NWAD or NWDD wait states that are programmed in the Bus Controller Region Table When there are no wait states in an access WAIT never goes active (5) N e Number of wait states inserted with READY (6) Output Data and or DT R may be driven indefinitely following a cycle if there is no subsequent bus activity (7) See Notes 1 2 and 3 (8) Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in order to be recognized and for proper operation However to guarantee recognition of the input at a particular edge of PCLK2 1 the setup times shown must be met Asynchronous inputs must be active for at least two consecutive PCLK2 1 rising edges to be seen by the processor (9) These specifications are guaranteed by the processor (10) These specifications must be met by the system for proper operation of the processor (11) This timing is dependent upon the loading of PCLK2 1 Use the derating curves of Section 4 5 3 to adjust the timing for PCLK2 1 loading (12) In the 1-x input clock mode the maximum input clock period is limited to 125 ns while the processor is operating When the processor is in reset the input clock may stop even in 1-x mode (13) When in the 1-x input clock mode these specifications assume a stable input clock with a period variation of less than g0 1% between adjacent cycles (14) In 2x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup and hold times to the falling edge of the CLKIN (See Figure 28a ) (15) In 1x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must be deasserted while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN (See Figure 28b )
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AC Characteristics 80960CF-16 (80960CF-16 only under the conditions described in Section 4 2 Operating Conditions and Section 4 5 1 AC Test Conditions ) (Continued)
Symbol TF TC TCS TCH TCL TCR TCF TCP T TPH TPL TPR TPF TOV TOH CLKIN Frequency CLKIN Period CLKIN Period Stability CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time OUTPUT CLOCKS(9) CLKIN to PCLK2 1 Delay PCLK2 1 Period PCLK2 1 High Time PCLK2 1 Low Time PCLK2 1 Rise Time PCLK2 1 Fall Time Output Valid Delay Output Hold TOV1 TOH1 A31 2 BE3 0 TOV2 TOH2 TOV3 TOH3 ADS WR TOV4 TOH4 TOV5 TOH5 D C SUP DMA BLAST WAIT TOV6 TOH6 TOV7 TOH7 DEN TOV8 TOH8 HOLDA BREQ LOCK TOV9 TOH9 DACK3 0 TOV10 TOH10 TOV11 TOH11 D31 0 DT R TOV12 TOH12 TOV13 TOH13 FAIL EOP3 0 TC3 0 TOV14 TOH14 Output Float for all outputs Input Setup TIS1 TIS2 TIS3 TIS4 Input Hold TIH1 TIH2 TIH3 TIH4 In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) (T 2) b 4 (T 2) b 4 1 1 SYNCHRONOUS OUTPUTS(10) (6 11) 3 3 6 3 4 5 3 4 4 4 3 T 2a3 2 3 3 SYNCHRONOUS INPUTS(10) TIS D31 0 BOFF BTERM READY HOLD D31 0 BOFF BTERM READY HOLD 5 21 9 9 5 7 2 5 ns ns ns ns ns ns ns ns (1 11) (1 11) (1 11) (1 11) (1 11) (1 11) (1 11) (1 11) 18 20 22 22 20 20 20 20 20 22 20 T 2 a 18 18 22 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
b2
Parameter INPUT CLOCK(10)
Min 0
Max 32 125 %
g0 1%
Units MHz ns ns D ns ns ns ns ns ns ns ns ns ns
Notes (1) (1 12) (1) (1 13) (1 12) (1) (1 12) (1) (1) (1) (1 3 13 14) (1 3) (1 13) (1 3) (1 13) (1 13) (1 3) (1 3)
In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x) In 1-x Mode (fCLK1x) In 2-x Mode (fCLK2x)
62 5 31 25 10 10 10 10 0 0
62 5 % 62 5 % 6 6 2 25 TC 2TC T2 T2 4 4
2
ns ns ns ns
(6 11) (6)
TOF
TIH
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AC Characteristics 80960CF-16 (80960CF-16 only under the conditions described in Section 4 2 Operating Conditions and Section 4 5 1 AC Test Conditions ) (Continued) Symbol TAVSH1 TAVSH2 TAVEL1 TAVEL2 TNLQV TDVNH TNLNH TNHQX TEHTV TTVEL TIS5 TIH5 TIS6 TIH6 TIS7 TIH7 TIS8 TIH8 Parameter A31 2 Valid to ADS Rising BE3 0 W R SUP D C DMA DACK3 0 Valid to ADS Rising A31 2 Valid to DEN Falling BE3 0 W R SUP INST DMA DACK3 0 Valid to DEN Falling WAIT Falling to Output Data Valid Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising Output Data Hold after WAIT Rising DT R Hold after DEN High DT R Valid to DEN Falling RESET Input Setup (2x Clock Mode) RESET Input Hold (2x Clock Mode) DREQ3 0 Input Setup DREQ3 0 Input Hold XINT7 0 NMI Input Setup XINT7 0 NMI Input Hold RESET Input Setup (1x Clock Mode) RESET Input Hold (1x Clock Mode) (N a 1) T 2b6 T 2b4 10 9 16 11 9 5 3 T 4a1 N Tb6 N Tg4 Tb6 (N a 1) T a 6 % T 2a4 Min RELATIVE OUTPUT TIMINGS(9 7) Tb4 Tb6 Tb6 Tb6
g6
Max Ta4 Ta6 Ta6 Ta6 N Ta6
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes
(4) (4) (5) (6) (7) (14) (14) (8) (8) (8) (8) (15) (15)
RELATIVE INPUT TIMINGS(7)
NOTES (1) See Section 4 5 2 AC Timing Waveforms for waveforms and definitions (2) See Figure 22 for capacitive derating information for output delays and hold times (3) See Figure 23 for capacitive derating information for rise and fall times (4) Where N is the number of NRAD NRDD NWAD or NWDD wait states that are programmed in the Bus Controller Region Table When there are no wait states in an access WAIT never goes active (5) N e Number of wait state inserted with READY (6) Output Data and or DT R may be driven indefinitely following a cycle if there is no subsequent bus activity (7) See Notes 1 2 and 3 (8) Since asynchronous inputs are synchronized internally by the 80960CF they have no required setup or hold times in order to be recognized and for proper operation However to guarantee recognition of the input at a particular edge of PCLK2 1 the setup times shown must be met Asynchronous inputs must be active for at least two consecutive PCLK2 1 rising edges to be seen by the processor (9) These specifications are guaranteed by the processor (10) These specifications must be met by the system for proper operation of the processor (11) This timing is dependent upon the loading of PCLK2 1 Use the derating curves of Figure 22 to adjust the timing for PCLK2 1 loading (12) In the 1-x input clock mode the maximum input clock period is limited to 125 ns while the processor is operating When the processor is in reset the input clock may stop even in 1-x mode (13) When in the 1-x input clock mode these specifications assume a stable input clock with a period variation of less than g0 1% between adjacent cycles (14) In 2x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must meet setup and hold times to the falling edge of the CLKIN (See Figure 28a ) (15) In 1x clock mode RESET is an asynchronous input which has no required setup and hold time for proper operation However to guarantee the device exits reset synchronized to a particular clock edge the RESET pin must be deasserted while CLKIN is high and meet setup and hold times to the rising edge of the CLKIN (See Figure 28b )
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The AC Specifications in Section 4 5 are tested with the 50 pf load shown in Figure 9 See Figure 16 to see how timings vary with load capacitance Specifications are measured at the 1 5V crossing point unless otherwise indicated Input waveforms are assumed to have a rise-and-fall time of s 2 ns from 0 8V to 2 0V See Section 4 5 2 AC Timing Waveforms for AC spec definitions test points and illustrations
CL e 50 pf for all signals
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451
AC TEST CONDITIONS
Figure 9 AC Test Load 452 AC TIMING WAVEFORMS
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Figure 10a Input and Output Clocks Waveform
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Figure 10b CLKIN Waveform
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Figure 11 Output Delay and Float Waveform
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Figure 12a Input Setup and Hold Waveform
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Figure 12b NMI XINT7 0 Input Setup and Hold Waveform
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Figure 13 Hold Acknowledge Timings
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Figure 14 Bus Back-Off (BOFF) Timings
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Figure 15 Relative Timings Waveforms 4 5 3 DERATING CURVES
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NOTE PCLK Load e 50 pF
Figure 16 Output Delay or Hold vs Load Capacitance
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(a) All outputs except LOCK DMA SUP HOLDA BREQ DACK3 0 EOP3 0 TC3 0 FAIL
(b) LOCK DMA EOP3 0 TC3 0 FAIL
SUP
HOLDA
BREQ
DACK3 0 271328 - 19
Figure 17 Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC
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Figure 18 ICC vs Frequency and Temperature
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The following table lists the condition of each processor output pin while HOLDA is asserted (low) Table 11 Hold Acknowledge and Backoff Conditions Pins A31 A2 D31 D0 BE3 0 WR ADS WAIT BLAST DT R DEN LOCK BREQ DC DMA SUP FAIL DACK3 DACK2 DACK1 DACK0 EOP TC3 EOP TC2 EOP TC1 EOP TC0 State During HOLDA Floating Floating Floating Floating Floating Floating Floating Floating Floating Floating Driven (high or low) Floating Floating Floating Driven high (Inactive) Driven high (Inactive) Driven high (Inactive) Driven high (Inactive) Driven high (Inactive) Driven if output Driven if output Driven if output Driven if output
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RESET BACKOFF AND HOLD ACKNOWLEDGE
The following table lists the condition of each processor output pin while RESET is asserted (low) Table 10 Reset Conditions Pins A31 A2 D31 D0 BE3 0 WR ADS WAIT BLAST DT R DEN LOCK BREQ DC DMA SUP FAIL DACK3 DACK2 DACK1 DACK0 EOP TC3 EOP TC2 EOP TC1 EOP TC0 State During Reset (HOLDA inactive)1 Floating Floating Driven high (Inactive) Driven low (Read) Driven high (Inactive) Driven high (Inactive) Driven low (Active) Driven low (Receive) Driven high (Inactive) Driven high (Inactive) Driven low (Inactive) Floating Floating Floating Driven low (Active) Driven high (Inactive) Driven high (Inactive) Driven high (Inactive) Driven high (Inactive) Floating (set to input mode) Floating (set to input mode) Floating (set to input mode) Floating (set to input mode)
NOTE (1) With regard to bus output pin state only the Hold Acknowledge state takes precedence over the reset state Although asserting the RESET pin will internally reset the processor the processor's bus output pins will not enter the reset state if it has granted Hold Acknowledge to a previous HOLD request (HOLDA is active) Furthermore the processor will grant new HOLD requests and enter the Hold Acknowledge state even while in reset For example if HOLDA is not active and the processor is in the reset state then HOLD is asserted the processor's bus pins will enter the Hold Acknowledge state and HOLDA will be granted The processor will not be able to perform memory accesses until the HOLD request is removed even if the RESET pin is brought high This operation is provided to simplify boot-up synchronization among multiple processors sharing the same bus
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BUS WAVEFORMS
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Figure 19 Cold Reset Waveform 36
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Figure 20 Warm Reset Waveform 37
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Figure 21 Entering the ONCE State 38
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NOTE Case 1 and Case 2 show two possible polarities of PCLK2 1
Figure 22a Clock Synchronization in the 2x Clock Mode
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NOTE In 1x clock mode the RESET pin is actually sampled on the falling edge of 2XCLK 2XCLK is an internal signal generated by the PLL and is not available on an external pin Therefore RESET is specified relative to the rising edge of CLKIN The RESET pin is sampled when PCLK is high
Figure 22b Clock Synchronization in the 1x Clock Mode
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Region Table Entry
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Figure 23 Non-Burst Non-Pipelined Requests without Wait States
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Region Table Entry
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Figure 24 Non-Burst Non-Pipelined Read Request with Wait States
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Region Table Entry
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Figure 25 Non-Burst Non-Pipelined Write Request with Wait States
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Region Table Entry
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Figure 26 Burst Non-Pipelined Read Request without Wait States 32-Bit Bus
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Region Table Entry
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Figure 27 Burst Non-Pipelined Read Request with Wait States 32-Bit Bus
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Region Table Entry
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Figure 28 Burst Non-Pipelined Write Request without Wait States 32-Bit Bus
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Region Table Entry
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Figure 29 Burst Non-Pipelined Write Request with Wait States 32-Bit Bus
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Region Table Entry
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Figure 30 Burst Non-Pipelined Read Request with Wait States 16-Bit Bus
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Region Table Entry
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Figure 31 Burst Non-Pipelined Read Request with Wait States 8-Bit Bus
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Region Table Entry
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Figure 32 Non-Burst Pipelined Read Request without Wait States 32-Bit Bus
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Region Table Entry
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Figure 33 Non-Burst Pipelined Read Request with Wait States 32-Bit Bus
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Region Table Entry
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Figure 34 Burst Pipelined Read Request without Wait States 32-Bit Bus
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Region Table Entry
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Figure 35 Burst Pipelined Read Requests with Wait States 32-Bit Bus
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Region Table Entry
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Figure 36 Burst Pipelined Read Requests with Wait States 16-Bit Bus
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Region Table Entry
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Figure 37 Burst Pipelined Read Requests with Wait States 8-Bit Bus
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Figure 38 Using External READY
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NOTE READY adds memory access time to data transfers whether or not the bus access is a burst access BTERM interrupts a bus access whether or not the bus access has more data transfers pending Either the READY signal or the BTERM signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access
Figure 39 Terminating a Burst with BTERM
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Figure 40 BOFF Functional Timing
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Figure 41 HOLD Functional Timing 57
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NOTES 1 Case 1 DREQ must deassert before DACK deasserts Applications are Fly-by and some packing and unpacking modes in which loads are followed by loads or stores are followed by stores 2 Case 2 DREQ must be deasserted by the second clock (rising edge) after DACK is driven high Applications are non fly-by transfers and adjacent load-stores or store-loads 3 DACKx is asserted for the duration of a DMA bus request The request may consist of multiple bus accesses (defined by ADS and BLAST Refer to User's Manual for ``access'' ``request'' definition
Figure 42 DREQ and DACK Functional Timing
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NOTE EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests EOP is NOT edge triggered EOP must be held for a minimum of 2 clock cycles then EOP must be deasserted within 15 clock cycles
Figure 43 EOP Functional Timing
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NOTE Terminal Count becomes active during the last bus request of a buffer transfer If the last LOAD STORE bus request is executed as multiple bus accesses the TC will be active for the entire bus request Refer to the User's Manual for further information
Figure 44 Terminal Count Functional Timing
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Figure 45 FAIL Functional Timing
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Figure 46 A Summary of Aligned and Unaligned Transfers for Little Endian Regions
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Figure 47 A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued)
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Figure 48 Idle Bus Operation 62
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